The present invention relates to a semiconductor device and a method of manufacturing the same and, in particular, to an effective technology when being applied to a semiconductor device and manufacturing thereof that are required for reducing a whole area of a semiconductor chip by reducing a size of a field effect transistor.
When field effect transistors used in various circuits constituting an SoC (System on Chip) are roughly classified according to circuit operation thereof, they can be classified into a low-voltage field effect transistor that has a thin gate insulating film and a short gate length and operates with a low voltage (for example, approximately 1.0 to 1.8 V), and a high-voltage field effect transistor that has a thick gate insulating film and a long gate length and operates with a high voltage (for example, approximately 3.3 to 5.0 V).
As a structure of the above-described low-voltage field effect transistor, for example, a fin-type has been proposed. For example, specification of U.S. Pat. No. 7,265,008 (Patent Document 1), specification of US Patent Application Publication No. 2005/0272190 (Patent Document 2), specification of US Patent Application Publication No. 2005/0153490 (Patent Document 3), specification of US Patent Application Publication No. 2009/0294874 (Patent Document 4), specification of U.S. Pat. No. 7,160,780 (Patent Document 5), specification of U.S. Pat. No. 7,851,340 (Patent Document 6), Japanese Patent Laid-Open No. 2011-14753 (Patent Document 7), and Japanese Patent Laid-Open No. 2011-9296 (Patent Document 8) disclose fin-type field effect transistors.
For example, Japanese Patent Laid-Open No. 2011-9296 (Patent Document 8) discloses a technology in which the fin-type field effect transistor has a plurality of fins formed on a first reference surface, and a plurality of fins formed on a second reference surface provided at a position higher than the first reference surface, and in which a distance between the two fins adjacent to each other with the first reference surface therebetween is formed larger than a distance between the two fins adjacent to each other with the second reference surface therebetween.
In addition, as the above-described high-voltage field effect transistor, there has been proposed, for example, a trench-type or a planar-type in which a concentration profile of a semiconductor region constituting a source/drain is optimized. For example, the specification of US Patent Application Publication No. 2008/0164514 (Patent Document 9) discloses a trench-type field effect transistor, and Japanese Patent Laid-Open No. 2002-270825 (Patent Document 10), Japanese Patent No. 4248548 (Patent Document 11), Japanese Patent Laid-Open No. 2005-353834 (Patent Document 12), Japanese Patent Laid-Open No. 2006-245548 (Patent Document 13), and Japanese Patent Laid-Open No. 2009-105421 (Patent Document 14) disclose the planar-type field effect transistor in which the concentration profile of the semiconductor region constituting the source/drain is optimized.